The present invention relates to a semiconductor integrated circuit, and more particularly to circuit technology applicable to a custom or customized semiconductor integrated circuit known as, for example, ASIC (Application Specific IC) as what is effective in improving the performance of such a semiconductor integrated circuit.
Japanese Patent Laid-Open No. 87362/1992 discloses a so-called multichip system in which a plurality of semiconductor integrated circuits are packaged on a circuit board. Obviously, not much improvement in a circuit-to-circuit signal transmission rate seems possible because the rate is determined by such physical conditions of the circuit board on which the integrated circuits are packaged as signal wiring resistance and parasitic capacity. However, with the progress of semiconductor integrated circuit technology resulting from the miniaturization of circuit elements, improvement in the operating speed of the semiconductor integrated circuit itself is conceivably possible. Granting that the individual semiconductor integrated circuit itself undergoes technological progress like this, the performance of the whole system is restricted by the signal transmission rate between semiconductor integrated circuits and thus unable to make sufficient improvement.
The present inventor has given elaborate study to the following subject so as to solve the problem of the operating speed gap between circuit blocks which will arise in some semiconductor integrated circuits.
A semiconductor integrated circuit such as what is called ASIC has a spread gate area as a circuit area for materializing the functions required by users. The spread gate area is an area whose function required is actually accomplished according to the form of connecting numerous basic circuits arranged repetitively. In this area, the transistor size is substantially uniformized and a necessary wiring area is provided anywhere beforehand; there is therefore a limit to increasing operating speed on the ground that the degree of integration therein is relatively low. On the other hand, macro cells may be employed in such a semiconductor integrated circuit to increase circuit integration. The macro cell is a circuit block which is predetermined to function as RAM or CPU and whose circuit arrangement or operating speed has been optimized. The macro cell is made with, for example, a functional block of RAM as a unit and mainly designed manually so that its density may be greater than that of any other circuit part such as a spread gate area. The progress of circuit and process technology has made it feasible to increase the operating speed of a circuit part like the macro cell considerably as compared with any other part formed in the spread gate area.
In order to utilize the operating performance of the whole semiconductor integrated circuit containing macro cells together with the spread gate area at its maximum, it is needless to say desirable for high-speed operation to be effected in each area as much as possible. Data corresponding to a plurality of operating cycles commensurate with the operating speed of the macro cell will have to be fed in parallel in accordance with the operating cycle of the spread gate area for the purpose. Moreover, the data corresponding to the plurality of operating cycles thus given in parallel will also have to be fed at the most suitable timing for the macro cell. However, it is still difficult meeting the necessities above only by inserting a multiplexer and a demultiplexer in the interface portion between the spread gate area and the macro cell.
Further, some selective function of the macro cell also allows the operating speed gap between the circuit blocks in the semiconductor integrated circuit to be practically absorbed. When, for example, the specification of reading and writing data in parallel from and to the RAM as the macro cell during one memory access cycle period in the spread gate area is to be satisfied, it may be satisfied by adopting a dual port RAM for the ram in question. At this time, the dual port RAM and the spread gate area may be operated at the same speed to meet the requirements. Since the macro cell is capable of operating at high speed as stated above, the function of the macro cell utilized in such a form is not sufficiently demonstrated. Moreover, the area occupied by the RAM having the plurality of ports tends to increase in size because its peripheral circuit becomes twice as large as that of a single port RAM. In view of making the macro cell capable of demonstrating its high-speed operating capability then, an additional circuit will be required to let the single port RAM macro cell perform read/write operations in time series in accordance with the read/write access cycles generated in parallel from the spread gate area.